module EXEMEM(CLK, reset,
	      pcjump_in, pcjump_out,
	      reg3_in, reg3_out,

	      reg_wen_in, reg_wen_out,
	      wb_sel_in, wb_sel_out,
	      reg_waddr_in,reg_waddr_out,

	      mem_wen_in, mem_wen_out,
	      isjeq_in, isjeq_out,
	      isjlt_in, 	isjlt_out,

	      aluresult_in,aluresult_out);


   input CLK;
   input reset;
   input [31:0] pcjump_in;
   reg [31:0]   pcjump;
   output [31:0] pcjump_out;
   assign pcjump_out = pcjump;

   input [31:0]  reg3_in;
   reg [31:0]    reg3;
   output [31:0] reg3_out;
   assign reg3_out = reg3;






   input         reg_wen_in;
   reg           reg_wen;
   output        reg_wen_out;
   assign reg_wen_out = reg_wen;

   input         wb_sel_in;
   reg           wb_sel;
   output        wb_sel_out;
   assign wb_sel_out = wb_sel;

   input [4:0]   reg_waddr_in;
   reg [4:0]     reg_waddr;
   output [4:0]  reg_waddr_out;
   assign reg_waddr_out = reg_waddr;






   input         mem_wen_in;
   reg           mem_wen;
   output        mem_wen_out;
   assign mem_wen_out = mem_wen;

   input         isjeq_in;
   reg           isjeq;
   output        isjeq_out;
   assign isjeq_out = isjeq;

   input         isjlt_in;
   reg           isjlt;
   output        isjlt_out;
   assign isjlt_out = isjlt;

   input [32:0]  aluresult_in;
   reg [32:0]    aluresult;
   output [32:0] aluresult_out;
   assign aluresult_out = aluresult;

   always@(posedge CLK or posedge reset)
     begin
        if (reset) begin
    	   pcjump   	<= 0;
    	   reg3 	<= 0;

    	   reg_wen <= 0;
    	   wb_sel 	<= 0;
    	   reg_waddr<=0;

    	   mem_wen <= 0;
    	   isjeq 	<= 0;
    	   isjlt   <= 0;
    	   aluresult <= 0;
        end else begin
    	   pcjump   	<= pcjump_in;
    	   reg3 	<= reg3_in;

    	   reg_wen <= reg_wen_in;
    	   wb_sel 	<= wb_sel_in;
    	   reg_waddr<=reg_waddr_in;

    	   mem_wen <= mem_wen_in;
    	   isjeq 	<= isjeq_in;
    	   isjlt   <= isjlt_in;
    	   aluresult <= aluresult_in;
        end
     end

endmodule
